1. Field of the Invention
The present invention relates to a liquid crystal display, and more particularly to a liquid crystal display and a driving method thereof that is adaptive for improving picture quality.
2. Description of the Related Art
Generally, a liquid crystal display (LCD) uses a pixel matrix arranged at intersections between gate lines and data lines to display a picture corresponding to video signals. Such a pixel consists of a liquid crystal cell controlling a transmitted light amount in accordance with a video signal, and a thin film transistor (TFT) for switching a video signal to be applied from the data line to the liquid crystal cell.
When a gate pulse is sequentially applied to the gate lines, a video signal is applied to the data lines. At this time, a desired voltage is supplied to a liquid crystal cell to which the gate pulse and the video signal are applied simultaneously, and a liquid crystal is driven with this voltage to thereby display a picture corresponding to the video signal. However, in such a conventional LCD, a charged voltage is differentiated depending upon a position of the liquid crystal cell.
In other words, when the same video signal is applied, a certain voltage Vg1 is charged in the liquid crystal cell positioned at an intersection between the first gate line GL1 and the first data line DL1 as shown in FIG. 1 and FIG. 2A. Otherwise, a voltage Vg2 lower than the certain voltage Vg1 is charged in the liquid crystal cell 4 positioned at an intersection between the first gate line GL1 and the nth data line DLn as shown in FIG. 2B.
As described above, in the conventional LCD, a voltage charged depending upon a position of the liquid crystal cell is differentiated due to a resistance voltage of the gate line GL and a capacitance value of the liquid crystal cell. Particularly, since such a phenomenon becomes more serious as LCDs move toward larger screens and a high resolution, picture quality of the LCD is deteriorated. In order to solve this problem, there has been suggested a driving method as shown in FIG. 3.
FIG. 3 shows a method of driving another conventional LCD.
Referring to FIG. 3, gate lines GL of another conventional LCD are supplied with two gate pulses GP1 and GP2. At one gate line GL, a first gate pulse GP1 is applied in such a manner so as to be synchronized with an nth horizontal synchronizing signal H while a second gate pulse GP2 is applied in such a manner to be synchronized with a (n+2)th horizontal synchronizing signal H.
In operation, when the second gate pulse GP2 is applied to the first gate line GL1, the first gate pulse GP1 is applied to the third gate line GL3. At this time, a certain voltage corresponding to a video signal is charged in the first gate line GL1. On the other hand, a voltage corresponding to the video signal at the first gate line GL1 is pre-charged in the third gate line GL3 supplied with the first gate pulse GP1.
For instance, if the second gate pulse Gp2 is applied to the first gate line GL1, then a voltage of 5V is pre-charged in the liquid crystal cells provided along the third gate line GL3 when a video signal having a voltage of 5V is supplied. Thereafter, if the second gate pulse GP2 is applied to the third gate line GL3, then only a voltage of 2V is charged in the liquid crystal cells provided along the third gate line GL3. In other words, in another conventional LCD driving method, when the first gate pulse GP1 is applied to the nth gate line GLn, a voltage corresponding to a video signal applied to the (n−2)th gate line GLn−2 is pre-charged, thereby charging a desired voltage irrespectively of the location of the liquid crystal cell.
FIG. 4 represents a gate driver for generating the gate pulse shown in FIG. 3.
Referring to FIG. 4, the conventional gate driver includes an OR gate 12 and a driver integrated circuit 14, hereinafter referred to as “D-IC”. Herein, a gate shift clock GSC is a signal for determining a time when the gate of the TFT is turned on or off. The gate start pulse GSP is a signal for indicating the first driving line of the field in one vertical synchronizing signal.
Flip-flops 6, 8 and 10 receive a gate shift clock signal GSC as shown in FIG. 6. When the liquid crystal display panel is driven, the gate start pulse GSP is inputted to the first flip-flop 6. The gate start pulse GSP inputted to the first flip-flop 6 is shifted into the second flip-flop 8 when the gate shift clock GSC is inputted. At this time, the gate start pulse GSP shifted into the second flip-flop 8 is applied to the OR gate 12. The gate start pulse GSP inputted to the OR gate 12 is applied to the D-IC 14.
Meanwhile, the gate start pulse GSP applied to the second flip-flop 8 is shifted into the third flip-flop 10 when the gate shift clock signal GSC is inputted. Further, the gate start pulse GSP applied to the third flip-flop 10 is applied to the OR gate 12 when the gate shift clock signal GSC is inputted. In other words, two gate start pulses GSP are inputted to the OR gate 12 at a desired time difference (i.e., one period of the gate shift clock signal GSC). Thus, the OR gate 12 applies two gate start pulse GSP2 to the D-IC 14 as shown in FIG. 6.
As shown in FIG. 5, the D-IC 14 includes an inverter 16 supplied with a gate output enable signal GOE, an AND gate 18 supplied with an output signal of the inverter 16 and two gate start pulse GSP2, and first and second switching devices SW1 and SW2 controlled by an output signal of the AND gate 18. The first switching device SW1 is connected to a first gate voltage source Vcc while the second switching device SW2 is connected to a second gate voltage source −Vg. Herein, the gate output enable signal GOE is a signal for controlling an output of the gate driver.
The AND gate 18 receives two gate start pulse GSP2 and a gate output enable signal GOE inverted by the inverter 16. At this time, the AND gate 18 applies a control signal of “1” to the first and second switching devices SW1 and SW2 when the gate start pulse GSP2 has a high state and when the gate output enable signal GOE passing through the inverter 16 has a high state. If a control signal of “1” is applied from the AND gate 18, then the first switching device SW1 is turned on to thereby output the first gate voltage Vcc to the gate line GL.
Thereafter, the AND gate 18 applies a control signal of “0” to the first and second switching devices SW1 and SW2 when the gate start pulse GSP2 has a low state or when the gate output enable signal GOE passing through the inverter 16 has a low state. If a control signal of “0” is applied from the AND gate 18, then the second switching device SW2 is turned on to thereby output the second gate voltage −Vg to the gate line GL. By repeating such a process, the first and second gate pulses GP1 and GP2 are sequentially outputted to the gate lines GL.
However, in another conventional LCD, when the gate pulse GP is fallen, a voltage charged in the liquid crystal cell is dropped by a voltage ΔV as shown in FIG. 7. In other words, when the gate pulse GP suddenly falls, a voltage charged in the liquid crystal cell is dropped by a voltage ΔV along the falling gate pulse GP. Accordingly, a desired voltage fails to be charged in the liquid crystal cell and hence a picture having a desired quality fails to be displayed on the LCD.